The present invention relates to a process for manufacturing floating gate non-volatile memory cells integrated on a semiconductor substrate which are incorporated in a cell matrix with an associated control circuitry. The process is compatible with salicide processes, and relates particularly, but not exclusively, to a process flow for manufacturing non-volatile memories, typically of the EPROM or Flash type, and electronic devices using salicide layers.
Reducing the size of elementary electronic devices (transistors, memory cells, etc.) involves lowering their supply voltage (Vdd). In turn, a lower supply voltage reflects a need to lower by an equal amount the threshold voltage (Vth) of the transistors so that a sufficient overdrive voltage can be provided.
The technological generations upwards of 0.35 mm featuring supply voltages below 3V require threshold values equal to or lower than 0.6V. Attaining these objectives is especially difficult where traditional CMOS processes are used in which the transistor gate regions are formed from N+ doped polysilicon overlaid with a layer which may comprise a metal layer, such as a salicide layer. This process involves forming buried channel transistors which features an inherent weakness with respect to leakage currents. For example, a buried channel P-channel transistor would have an N+ gate in an opposite implanted substrate.
In general, for technological generations of 0.35 mm and up, a salicide process (self-aligned silicide) is used. This process provides dual gate transistors, i.e., N-channel transistors with an N+ gate region and P-channel transistors with a P+ gate region. In this way, the P-channel transistors can be formed as mirror images of the N-channel transistors, again with no opposite-implantations. Thus, the advantage of low threshold values can be secured at the same time as the leakage and punch-through problems are minimized.
Briefly, the process of manufacturing dual gate transistors using salicide layers comprises forming initially an undoped polysilicon layer isolated from a semiconductor substrate by an oxide layer to produce the gate regions. After a patterning of the polysilicon gate regions by a photolithographic technique, two appropriate masks are used to carry out the LDD implantations (Nxe2x88x92 and Pxe2x88x92) for N-channel and P-channel transistors to form first lightly doped portions of the junction areas (source/drain regions) of the transistors.
Spacers are then formed on the side walls of each transistor gate region. At this step, the heavy implantations (N+ and P+) for the junction areas are carried out, again using two masks. These implants form second heavily doped portions of the source/drain regions while simultaneously doping the gate polysilicon which will be N+ for the N-channel transistors and P+ for the P-channel transistors.
The process further comprises activating the implanted dopant species by an appropriate thermal treatment, and depositing a thin metal layer (e.g., Ti/TiN). The last-mentioned layer is then reacted with the silicon of the junction and gate areas by a suitable thermal treatment to produce so-called salicide layers (e.g., TiSi2). The unreacted metal still present in the oxide zones at the spacers or on field oxide, for example, is subsequently selectively removed using an appropriate chemical solution.
In the salicide process, the metal layers are self-aligned to the junction areas and the gate regions. Consequently, compared to a conventional process, the salicide process also allows the series resistances of the junction areas to be reduced, thereby achieving faster performance. At the same time, by having the N+ and P+ implantations carried out before the metal layer is formed over the gate region, the salicide process can be best integrated to the process of forming dual gate regions.
To complete the description of a typical salicide layer forming process, it remains to be said that it is nearly always necessary to prevent the formation inside a device of salicide over certain structures, such as ESD protection structures, for example. Just prior to depositing the metal layer to be reacted with the silicon (e.g., titanium or titanium nitride Ti/TiN), a thin material layer is usually deposited to prevent the salicide phase from forming. The thin material layer may be a layer of oxide or nitride. This layer is then removed selectively by masking (Siprot mask) all those regions where the formation of the salicide layer is required. These regions protect the zones where the metal/silicon reaction should not be prevented.
As said above, the salicide process is widely used for producing advanced CMOS logic processes for the manufacture of microprocessors and microcontrollers and which require, component-wise, that only N-channel and P-channel transistors be provided. Integrating additional components, such as DRAM cells or non-volatile EPROM or Flash-EPROM cells, in such processes is instead a more innovative field.
Semiconductor integrated electronic memory devices of the EPROM or Flash-EPROM type comprise a plurality of non-volatile memory cells organized in matrix form, i.e. into rows or word lines and columns or bit lines. Each non-volatile memory cell comprises a MOS transistor having a floating gate electrode above the channel region. That is, a gate electrode showing a high impedance to all the other terminals of the cell itself and of the circuit in which it is connected. The cell also has a second electrode called the control gate which is coupled to the floating gate electrode, and is driven by appropriate control voltages. The other transistor electrodes are the customary drain and source junction terminals.
Integrating such memory cells to a salicide process has some disadvantages, including those listed below. The presence of salicide over the cell junctions can result in increased junction leakage current. Forming salicide in the memory cell may prove difficult and, therefore, hardly reproducible due to the small dimensions of the geometries. This is especially so at the gate (word line).
In the memory cells, both before the deposition of a first metal layer and after the reaction with the silicon that forms the salicide layer, the thick oxide layer which has been grown thereover during the oxidation step must be removed. The thick oxide layer seals the cell. This removal, when performed in a blanketing manner (i.e., everywhere), may degrade the characteristics of the transistor junctions from which such a deep removal would be unnecessary. Alternatively, an additional masking step would have to be carried out to remove the oxide layer from the cell region only.
A first technical approach to these problems provides a process flow whereby the salicide can only be formed in the peripheral zones of a memory device (transistors, resistors, etc.) and not in the memory cell matrix zone. Using the Siprot mask, the physical removal of salicide from the matrix zone can be easily achieved by protecting the matrix with the mask.
While being in many ways advantageous, this first approach has some drawbacks. In fact, without the salicide layer in the memory matrix, a way must be found of ensuring a minimum level of resistivity for the layer which comprises the word lines, i.e., the long strips to which the gates of the cells situated in a given matrix row belong. By providing a metal level useful to produce periodical contacting of the word lines, the so-called wordline strapping or shunting resistances in the range of 100 ohms become compatible with a contact of the metal layer to the word line every 256 cells. These resistances can be obtained by heavily doping the polysilicon layer that comprises the word line using concentrations in excess of 1E20 atoms/cm3, for example.
Since blanket doping of the polysilicon is not feasible, this heavy doping in the matrix zone alone can be obtained by using an additional mask and a heavy ion implantation step, e.g., a P dosage of about 1E16 atoms/cm3. The polysilicon should be suitably doped N+ or P+ according to the zones. However, this a very expensive approach.
A second approach comprises re-implanting the matrix zone during the implantation of the N+ junctions of the transistors. This approach has an advantage in that it introduces no additional steps, but also has an obvious disadvantage. The transistor N+ implantations usually are not optimized both in dosage and energy values for their introduction to the matrix. Thus, a fraction of the implanted dosage might pass through the thin residual insulation oxide layer which separates the drain regions of the various cells, and short-circuit adjacent columns (bit lines).
An object of the present invention is to provide a process for manufacturing non-volatile memory cells incorporated in matrices with associated circuitry using salicide technology to minimize the process steps and overcome the limitations and drawbacks of conventional processes.
The concept behind this invention is one of having the cell gate regions, and hence the word lines of the memory cell matrix, doped by a heavily doped polysilicon layer which is deposited after the interpoly layer of the matrix. This layer is then removed from the circuitry associated with the matrix without involving any additional process steps.
More particularly, the process includes forming a plurality of active areas in the semiconductor substrate for the cell matrix and the control circuitry, forming a first dielectric layer and a first polysilicon layer on the active areas to produce floating gate regions for the memory cells, forming a second dielectric layer on the first polysilicon layer, and forming a second polysilicon layer on the first polysilicon layer.
The process preferably further includes doping the second polysilicon layer to reduce a resistance thereof, and removing the second polysilicon layer, the second dielectric layer, the first polysilicon layer, and the first oxide layer from the active areas for the control circuitry using a first mask. At least one additional oxide layer and a third undoped polysilicon layer is preferably formed on the active areas for the control circuitry and on the second polysilicon layer.
The third polysilicon layer is preferably defined to produce gate regions for the MOS transistors of the control circuitry using a second mask while removing the third polysilicon layer from the active areas for the cell matrix. A self-aligned etching step is preferably performed above the active areas for the cell matrix to define gates for the memory cells using a third mask protecting the active areas for the control circuitry. Dopants may be implanted in junction areas to produce source/drain regions for the memory cells.